v0.8.6 - Sub-Cycle Accuracy Improvements (M11 S3-S5) Phase 1.5 Milestone 11 Sub-Cycle Accuracy - 83% complete (Sprints 3-5) Key Features: - DMC DMA Cycle Stealing: CPU stalls 4 cycles per DMC sample fetch - Open Bus Behavior: last_bus_value tracks data bus state - Controller Open Bus: Bits 5-7 mixed from open bus - Per-Cycle Mapper Clocking: mapper.clock(1) in on_cpu_cycle() Test Results: - 522+ tests passing (0 failures, 1 ignored) - 100% Blargg pass rate (90/90 tests) - 2 new open bus behavior tests