Commit aac5eba6 authored by Libretro-Admin's avatar Libretro-Admin
Browse files
parent 30da0c55
Pipeline #19863 passed with stages
in 3 minutes and 28 seconds
......@@ -14,6 +14,7 @@ SOURCES_CXX := \
$(CORE_DIR)/core/hw/arm7/arm64.cpp \
$(CORE_DIR)/core/hw/arm7/arm7.cpp \
$(CORE_DIR)/core/hw/arm7/virt_arm.cpp \
$(CORE_DIR)/core/hw/arm7/vbaARM.cpp \
\
$(CORE_DIR)/core/hw/aica/dsp.cpp \
$(CORE_DIR)/core/hw/aica/dsp_arm64.cpp \
......
......@@ -88,7 +88,7 @@ const int AICA_TICK = 145125; // 44.1 KHz / 32
static int AicaUpdate(int tag, int c, int j)
{
arm_Run(32);
aicaarm::run(32);
if (!settings.aica.NoBatch && !settings.aica.DSPEnabled)
AICA_Sample32();
......
......@@ -111,7 +111,7 @@ u32 ReadMem_aica_reg(u32 addr,u32 sz)
static void ArmSetRST()
{
ARMRST &= 1;
arm_SetEnabled(ARMRST == 0);
aicaarm::enable(ARMRST == 0);
}
void WriteMem_aica_reg(u32 addr,u32 data,u32 sz)
{
......
......@@ -79,7 +79,7 @@ void arm_Run_(u32 CycleCount)
}
}
void arm_Run(u32 samples)
void aicaarm::run(u32 samples)
{
for (u32 i = 0; i < samples; i++)
{
......@@ -91,12 +91,12 @@ void arm_Run(u32 samples)
void armt_init();
void arm_Init()
void aicaarm::init()
{
#if FEAT_AREC != DYNAREC_NONE
armt_init();
#endif
arm_Reset();
aicaarm::reset();
for (int i = 0; i < 256; i++)
{
......@@ -275,7 +275,7 @@ void CPUUndefinedException()
void FlushCache();
void arm_Reset()
void aicaarm::reset()
{
DEBUG_LOG(AICA_ARM, "AICA ARM Reset");
#if FEAT_AREC != DYNAREC_NONE
......@@ -339,16 +339,14 @@ void CPUFiq()
#include "hw/sh4/sh4_core.h"
void arm_SetEnabled(bool enabled)
void aicaarm::enable(bool enabled)
{
if(!Arm7Enabled && enabled)
arm_Reset();
aicaarm::reset();
Arm7Enabled=enabled;
}
void update_armintc()
{
reg[INTR_PEND].I=e68k_out && armFiqEnable;
......@@ -1534,7 +1532,7 @@ void armv_MOV32(eReg regn, u32 imm)
#endif
//Run a timeslice for ARMREC
void arm_Run(u32 samples)
void aicaarm::run(u32 samples)
{
for (int i = 0; i < samples; i++)
{
......
#pragma once
#include "types.h"
void arm_Init();
void arm_Reset();
void arm_Run(u32 samples);
void arm_SetEnabled(bool enabled);
namespace aicaarm {
void init();
void reset();
void run(u32 samples);
void enable(bool enabled);
enum
}
enum Arm7Reg
{
RN_CPSR = 16,
RN_SPSR = 17,
......
// nullAICA.cpp : Defines the entry point for the DLL application.
//
#include "arm7.h"
//called when plugin is used by emu (you should do first time init here)
s32 libARM_Init()
{
aicaarm::init();
return 0;
}
//called when plugin is unloaded by emu, only if dcInit is called (eg, not called to enumerate plugins)
void libARM_Term()
{
//arm7_Term ?
}
//It's supposed to reset anything
void libARM_Reset(bool hard)
{
aicaarm::reset();
aicaarm::enable(false);
}
#pragma once
#include "types.h"
#include "ta_structs.h"
enum
......
#include "ta.h"
#include "ta_ctx.h"
#include "spg.h"
#include "oslib/oslib.h"
#include "hw/sh4/sh4_sched.h"
......
......@@ -13,6 +13,7 @@
#include "sh4_interrupts.h"
#include "sh4_core.h"
#include "sh4_mmr.h"
#include "oslib/oslib.h"
/*
......
......@@ -26,6 +26,7 @@
#include <sys/param.h>
#include <sys/time.h>
#include <unistd.h>
#include "oslib/host_context.h"
#include "hw/sh4/dyna/blockmanager.h"
#include "hw/mem/vmem32.h"
......@@ -183,24 +184,6 @@ void setup_seh(void)
#endif
#endif
struct rei_host_context_t
{
#if HOST_CPU != CPU_GENERIC
size_t pc;
#endif
#if HOST_CPU == CPU_X86
u32 eax;
u32 ecx;
u32 esp;
#elif HOST_CPU == CPU_ARM
u32 r[15];
#elif HOST_CPU == CPU_ARM64
u64 x2;
#endif
};
#define MCTX(p) (((ucontext_t *)(segfault_ctx))->uc_mcontext p)
template <typename Ta, typename Tb>
......@@ -212,7 +195,7 @@ static void bicopy(Ta& rei, Tb& seg, bool to_segfault)
rei = seg;
}
static void context_segfault(rei_host_context_t* reictx, void* segfault_ctx, bool to_segfault)
static void context_segfault(host_context_t* reictx, void* segfault_ctx, bool to_segfault)
{
#if !defined(TARGET_NO_EXCEPTIONS)
#if HOST_CPU == CPU_ARM
......@@ -259,12 +242,12 @@ static void context_segfault(rei_host_context_t* reictx, void* segfault_ctx, boo
#endif
}
static void context_from_segfault(rei_host_context_t* reictx, void* segfault_ctx)
static void context_from_segfault(host_context_t* reictx, void* segfault_ctx)
{
context_segfault(reictx, segfault_ctx, false);
}
static void context_to_segfault(rei_host_context_t* reictx, void* segfault_ctx)
static void context_to_segfault(host_context_t* reictx, void* segfault_ctx)
{
context_segfault(reictx, segfault_ctx, true);
}
......@@ -278,7 +261,7 @@ bool BM_LockedWrite(u8* address);
#ifdef __MACH__
static void sigill_handler(int sn, siginfo_t * si, void *segfault_ctx)
{
rei_host_context_t ctx;
host_context_t ctx;
context_from_segfault(&ctx, segfault_ctx);
......@@ -307,7 +290,7 @@ extern "C" char __start__;
static void signal_handler(int sn, siginfo_t * si, void *segfault_ctx)
{
rei_host_context_t ctx;
host_context_t ctx;
context_from_segfault(&ctx, segfault_ctx);
......@@ -769,4 +752,4 @@ void __libnx_exception_handler(ThreadExceptionDump *ctx)
}
}
#endif
\ No newline at end of file
#endif
......@@ -38,10 +38,6 @@ extern char *game_data;
extern bool boot_to_bios;
extern bool reset_requested;
extern void init_mem();
extern void arm_Init();
extern void term_mem();
/*
libndc
......@@ -87,8 +83,8 @@ s32 plugins_Init()
if (s32 rv = libAICA_Init())
return rv;
init_mem();
arm_Init();
if (s32 rv = libARM_Init())
return rv;
//if (s32 rv = libExtDevice_Init())
// return rv;
......@@ -103,7 +99,6 @@ void plugins_Term(void)
//term all plugins
//libExtDevice_Term();
term_mem();
//arm7_Term ?
libAICA_Term();
......@@ -116,9 +111,7 @@ void plugins_Reset(bool hard)
libPvr_Reset(hard);
libGDR_Reset(hard);
libAICA_Reset(hard);
arm_Reset();
arm_SetEnabled(false);
libARM_Reset(hard);
//libExtDevice_Reset(Manual);
}
......
#pragma once
#include "types.h"
void WriteSample(s16 right, s16 left);
constexpr u32 SAMPLE_COUNT = 512;
#pragma once
#include "types.h"
struct host_context_t {
#if HOST_CPU != CPU_GENERIC
size_t pc;
#endif
#if HOST_CPU == CPU_X86
u32 eax;
u32 ecx;
u32 esp;
#elif HOST_CPU == CPU_ARM
u32 r[15];
#elif HOST_CPU == CPU_ARM64
u64 x2;
#endif
};
#pragma once
#include "types.h"
double os_GetSeconds();
void os_DoEvents();
#ifdef _MSC_VER
#include <intrin.h>
#endif
u32 static INLINE bitscanrev(u32 v)
{
#ifdef __GNUC__
return 31-__builtin_clz(v);
#else
unsigned long rv;
_BitScanReverse(&rv,v);
return rv;
#endif
}
void os_DebugBreak();
#pragma once
#include "oslib/oslib.h"
#include "hw/pvr/Renderer_if.h"
#include <algorithm>
......
......@@ -726,6 +726,11 @@ static void libExtDevice_WriteMem_A0_010(u32 addr,u32 data,u32 size) { }
static u32 libExtDevice_ReadMem_A5(u32 addr,u32 size){ return 0; }
static void libExtDevice_WriteMem_A5(u32 addr,u32 data,u32 size) { }
//ARM
s32 libARM_Init();
void libARM_Reset(bool hard);
void libARM_Term();
template<u32 sz>
u32 ReadMemArr(u8 *array, u32 addr)
{
......@@ -769,26 +774,6 @@ struct OnLoad
OnLoad(OnLoadFP* fp) { fp(); }
};
void os_DoEvents();
double os_GetSeconds();
#ifdef _MSC_VER
#include <intrin.h>
#endif
u32 static INLINE bitscanrev(u32 v)
{
#ifdef _MSC_VER
unsigned long rv;
_BitScanReverse(&rv,v);
return rv;
#else
return 31-__builtin_clz(v);
#endif
}
void os_DebugBreak(void);
bool ra_serialize(const void *src, unsigned int src_size, void **dest, unsigned int *total_size) ;
bool ra_unserialize(void *src, unsigned int src_size, void **dest, unsigned int *total_size);
bool dc_serialize(void **data, unsigned int *total_size);
......
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