Commit ee9cd16f authored by Flyinghead's avatar Flyinghead
Browse files

arm/linux/gles2 fixes

parent 01305795
......@@ -7,7 +7,7 @@ NO_THREADS := 1
NO_EXCEPTIONS := 0
NO_NVMEM := 0
NO_VERIFY := 1
HAVE_LTCG := 1
HAVE_LTCG := 0
HAVE_GENERIC_JIT := 1
HAVE_GL3 := 0
FORCE_GLES := 0
......@@ -152,6 +152,7 @@ else ifneq (,$(findstring rpi,$(platform)))
GLES = 1
GL_LIB := -L/opt/vc/lib -lbrcmGLESv2
INCFLAGS += -I/opt/vc/include
CFLAGS += -DTARGET_NO_STENCIL
else
FORCE_GLES = 1
endif
......@@ -460,7 +461,7 @@ else ifneq (,$(findstring osx,$(platform)))
GL_LIB := -framework OpenGL
else ifneq (,$(findstring ios,$(platform)))
GL_LIB := -framework OpenGLES
else
else ifeq ($(GL_LIB),)
GL_LIB := -lGL
endif
......
DEPS_DIR = $(CORE_DIR)/deps
LIBRETRO_COMM_DIR = $(CORE_DIR)/libretro-common
INCFLAGS := -I$(CORE_DIR)/libretro \
INCFLAGS += -I$(CORE_DIR)/libretro \
-I$(CORE_DIR) \
-I$(DEPS_DIR) \
-I$(LIBRETRO_COMM_DIR)/include
......@@ -10,8 +10,10 @@ CORE_DEFINES += -DNO_MMU
SOURCES_C :=
SOURCES_CXX := \
$(CORE_DIR)/hw/arm7/arm7.cpp \
$(CORE_DIR)/hw/arm7/arm_mem.cpp \
$(CORE_DIR)/hw/arm7/arm7.cpp \
$(CORE_DIR)/hw/arm7/vbaARM.cpp \
$(CORE_DIR)/hw/arm7/virt_arm.cpp \
\
$(CORE_DIR)/hw/aica/dsp.cpp \
$(CORE_DIR)/hw/aica/dsp_interp.cpp \
......
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#pragma once
#include "types.h"
#include "hw/aica/aica.h"
#define REG_L (0x2D00)
#define REG_M (0x2D04)
enum
{
RN_CPSR = 16,
RN_SPSR = 17,
R13_IRQ = 18,
R14_IRQ = 19,
SPSR_IRQ = 20,
R13_USR = 26,
R14_USR = 27,
R13_SVC = 28,
R14_SVC = 29,
SPSR_SVC = 30,
R13_ABT = 31,
R14_ABT = 32,
SPSR_ABT = 33,
R13_UND = 34,
R14_UND = 35,
SPSR_UND = 36,
R8_FIQ = 37,
R9_FIQ = 38,
R10_FIQ = 39,
R11_FIQ = 40,
R12_FIQ = 41,
R13_FIQ = 42,
R14_FIQ = 43,
SPSR_FIQ = 44,
RN_PSR_FLAGS = 45,
R15_ARM_NEXT = 46,
INTR_PEND = 47,
CYCL_CNT = 48,
RN_ARM_REG_COUNT
};
typedef union
{
struct
{
u8 B0;
u8 B1;
u8 B2;
u8 B3;
} B;
struct
{
u16 W0;
u16 W1;
} W;
union
{
struct
{
u32 _pad0 : 28;
u32 V : 1; //Bit 28
u32 C : 1; //Bit 29
u32 Z : 1; //Bit 30
u32 N : 1; //Bit 31
};
struct
{
u32 _pad1 : 28;
u32 NZCV : 4; //Bits [31:28]
};
} FLG;
struct
{
u32 M : 5; //mode, PSR[4:0]
u32 _pad0 : 1; //not used / zero
u32 F : 1; //FIQ disable, PSR[6]
u32 I : 1; //IRQ disable, PSR[7]
u32 _pad1 : 20; //not used / zero
u32 NZCV : 4; //Bits [31:28]
} PSR;
u32 I;
} reg_pair;
extern bool armFiqEnable;
extern DECL_ALIGN(8) reg_pair arm_Reg[RN_ARM_REG_COUNT];
void arm_Init();
void arm_Reset();
void arm_Run(u32 uNumCycles);
void arm_SetEnabled(bool enabled);
u32 sh4_ReadMem_reg(u32 addr,u32 size);
void sh4_WriteMem_reg(u32 addr,u32 data,u32 size);
#define arm_sh4_bias (2)
void init_mem();
void term_mem();
#include "arm_mem.h"
#include "arm7.h"
#include "types.h"
#include "hw/aica/aica_if.h"
#define REG_L (0x2D00)
#define REG_M (0x2D04)
//Set to true when aica interrupt is pending
bool aica_interr=false;
u32 aica_reg_L=0;
//Set to true when the out of the intc is 1
bool e68k_out = false;
u32 e68k_reg_L = 0;
u32 e68k_reg_M = 0; //constant ?
void update_e68k(void)
{
if (!e68k_out && aica_interr)
{
//Set the pending signal
//Is L register held here too ?
e68k_out=1;
e68k_reg_L=aica_reg_L;
update_armintc();
}
}
void libARM_InterruptChange(u32 bits,u32 L)
{
aica_interr=bits!=0;
if (aica_interr)
aica_reg_L=L;
update_e68k();
}
void e68k_AcceptInterrupt(void)
{
e68k_out=false;
update_e68k();
update_armintc();
}
//Reg reads from arm side ..
template <u32 sz,class T>
T arm_ReadReg(u32 addr)
{
addr&=0x7FFF;
switch (addr)
{
case REG_L:
return e68k_reg_L;
case REG_M:
return e68k_reg_M; //shouldn't really happen
default:
break;
}
return libAICA_ReadReg(addr,sz);
}
template <u32 sz,class T>
void arm_WriteReg(u32 addr,T data)
{
addr &= 0x7FFF;
switch (addr)
{
case REG_L:
return; // Shouldn't really happen (read only)
case REG_M:
//accept interrupts
if (data & 1)
e68k_AcceptInterrupt();
break;
default:
break;
}
return libAICA_WriteReg(addr, data, sz);
}
//00000000~007FFFFF @DRAM_AREA*
//00800000~008027FF @CHANNEL_DATA
//00802800~00802FFF @COMMON_DATA
//00803000~00807FFF @DSP_DATA
template u8 arm_ReadReg<1,u8>(u32 adr);
template u16 arm_ReadReg<2,u16>(u32 adr);
template u32 arm_ReadReg<4,u32>(u32 adr);
template void arm_WriteReg<1>(u32 adr,u8 data);
template void arm_WriteReg<2>(u32 adr,u16 data);
template void arm_WriteReg<4>(u32 adr,u32 data);
#include "arm_mem.h"
#include "arm7.h"
#include "types.h"
#include "hw/aica/aica_if.h"
#define REG_L (0x2D00)
#define REG_M (0x2D04)
//Set to true when aica interrupt is pending
bool aica_interr=false;
u32 aica_reg_L=0;
//Set to true when the out of the intc is 1
bool e68k_out = false;
u32 e68k_reg_L;
u32 e68k_reg_M=0; //constant ?
void update_e68k()
{
if (!e68k_out && aica_interr)
{
//Set the pending signal
//Is L register held here too ?
e68k_out=1;
e68k_reg_L=aica_reg_L;
update_armintc();
}
}
void libARM_InterruptChange(u32 bits,u32 L)
{
aica_interr=bits!=0;
if (aica_interr)
aica_reg_L=L;
update_e68k();
}
void e68k_AcceptInterrupt()
{
e68k_out=false;
update_e68k();
update_armintc();
}
//Reg reads from arm side ..
template <u32 sz,class T>
T arm_ReadReg(u32 addr)
{
addr&=0x7FFF;
if (addr==REG_L)
return e68k_reg_L;
else if(addr==REG_M)
return e68k_reg_M; //shouldn't really happen
else
return libAICA_ReadReg(addr,sz);
}
template <u32 sz,class T>
void arm_WriteReg(u32 addr,T data)
{
addr &= 0x7FFF;
if (addr == REG_L)
{
return; // Shouldn't really happen (read only)
}
else if (addr == REG_M)
{
//accept interrupts
if (data & 1)
e68k_AcceptInterrupt();
}
else
{
return libAICA_WriteReg(addr, data, sz);
}
}
//00000000~007FFFFF @DRAM_AREA*
//00800000~008027FF @CHANNEL_DATA
//00802800~00802FFF @COMMON_DATA
//00803000~00807FFF @DSP_DATA
template u8 arm_ReadReg<1,u8>(u32 adr);
template u16 arm_ReadReg<2,u16>(u32 adr);
template u32 arm_ReadReg<4,u32>(u32 adr);
template void arm_WriteReg<1>(u32 adr,u8 data);
template void arm_WriteReg<2>(u32 adr,u16 data);
template void arm_WriteReg<4>(u32 adr,u32 data);
\ No newline at end of file
#pragma once
#include "types.h"
#include "hw/aica/aica_if.h"
template <u32 sz,class T>
T arm_ReadReg(u32 addr);
template <u32 sz,class T>
void arm_WriteReg(u32 addr,T data);
/* TODO/FIXME - might need to cleanup */
//Set to true when the out of the intc is 1
extern bool e68k_out;
extern u32 e68k_reg_L;
extern u32 e68k_reg_M;
static INLINE u8 DYNACALL ReadMemArm1(u32 addr)
{
addr&=0x00FFFFFF;
if (addr<0x800000)
return *(u8*)&aica_ram.data[addr&(ARAM_MASK)];
addr&=0x7FFF;
switch (addr)
{
case REG_L:
return e68k_reg_L;
case REG_M:
return e68k_reg_M; //shouldn't really happen
default:
break;
}
return libAICA_ReadReg(addr,1);
}
static INLINE u16 DYNACALL ReadMemArm2(u32 addr)
{
addr&=0x00FFFFFF;
if (addr<0x800000)
return *(u16*)&aica_ram.data[addr&(ARAM_MASK-(1))];
addr&=0x7FFF;
switch (addr)
{
case REG_L:
return e68k_reg_L;
case REG_M:
return e68k_reg_M; //shouldn't really happen
default:
break;
}
return libAICA_ReadReg(addr,2);
}
static INLINE u32 DYNACALL ReadMemArm4(u32 addr)
{
addr&=0x00FFFFFF;
if (addr<0x800000)
{
u32 rv=*(u32*)&aica_ram.data[addr&(ARAM_MASK-(3))];
if (unlikely(addr&3))
{
u32 sf=(addr&3)*8;
return (rv>>sf) | (rv<<(32-sf));
}
return rv;
}
addr&=0x7FFF;
switch (addr)
{
case REG_L:
return e68k_reg_L;
case REG_M:
return e68k_reg_M; //shouldn't really happen
default:
break;
}
return libAICA_ReadReg(addr,4);
}
static INLINE void DYNACALL WriteMemArm1(u32 addr,u8 data)
{
addr&=0x00FFFFFF;
if (addr<0x800000)
{
*(u8*)&aica_ram.data[addr&(ARAM_MASK)]=data;
return;
}
arm_WriteReg<1,u8>(addr,data);
}
static INLINE void DYNACALL WriteMemArm2(u32 addr,u16 data)
{
addr&=0x00FFFFFF;
if (addr<0x800000)
{
*(u16*)&aica_ram.data[addr&(ARAM_MASK-(1))]=data;
return;
}
arm_WriteReg<2,u16>(addr,data);
}
static INLINE void DYNACALL WriteMemArm4(u32 addr,u32 data)
{
addr&=0x00FFFFFF;
if (addr<0x800000)
{
*(u32*)&aica_ram.data[addr&(ARAM_MASK-(3))]=data;
return;
}
arm_WriteReg<4,u32>(addr,data);
}
#define arm_ReadMem8 ReadMemArm1
#define arm_ReadMem16 ReadMemArm2
#define arm_ReadMem32 ReadMemArm4
#define arm_WriteMem8 WriteMemArm1
#define arm_WriteMem16 WriteMemArm2
#define arm_WriteMem32 WriteMemArm4
extern bool e68k_out;
#define update_armintc() arm_Reg[INTR_PEND].I=e68k_out && armFiqEnable
#pragma once
#include "types.h"
#include "hw/aica/aica_if.h"
template <u32 sz,class T>
T arm_ReadReg(u32 addr);
template <u32 sz,class T>
void arm_WriteReg(u32 addr,T data);
template<int sz,typename T>
static inline T DYNACALL ReadMemArm(u32 addr)
{
addr&=0x00FFFFFF;
if (addr<0x800000)
{
T rv=*(T*)&aica_ram[addr&(ARAM_MASK-(sz-1))];
if (unlikely(sz==4 && addr&3))
{
u32 sf=(addr&3)*8;
return (rv>>sf) | (rv<<(32-sf));
}
else
return rv;
}
else
{
return arm_ReadReg<sz,T>(addr);
}
}
template<int sz,typename T>
static inline void DYNACALL WriteMemArm(u32 addr,T data)
{
addr&=0x00FFFFFF;
if (addr<0x800000)
{
*(T*)&aica_ram[addr&(ARAM_MASK-(sz-1))]=data;
}
else
{
arm_WriteReg<sz,T>(addr,data);
}
}
#define arm_ReadMem8 ReadMemArm<1,u8>
#define arm_ReadMem16 ReadMemArm<2,u16>
#define arm_ReadMem32 ReadMemArm<4,u32>
#define arm_WriteMem8 WriteMemArm<1,u8>
#define arm_WriteMem16 WriteMemArm<2,u16>
#define arm_WriteMem32 WriteMemArm<4,u32>
u32 sh4_ReadMem_reg(u32 addr,u32 size);
void sh4_WriteMem_reg(u32 addr,u32 data,u32 size);
void init_mem();
void term_mem();
#define aica_reg_16 ((u16*)aica_reg)
#define AICA_RAM_SIZE (ARAM_SIZE)
#define AICA_RAM_MASK (ARAM_MASK)
#define AICA_MEMMAP_RAM_SIZE (8*1024*1024) //this is the max for the map, the actual ram size is AICA_RAM_SIZE
#define AICA_MEMMAP_RAM_MASK (AICA_MEMMAP_RAM_SIZE-1)
extern bool e68k_out;
void update_armintc();
\ No newline at end of file
//{{NO_DEPENDENCIES}}
// Microsoft Visual C++ generated include file.
// Used by sdlAICA.rc
//
#define IDD_SETTINGS 101
#define IDD_DIALOG1 102
#define IDD_DEBUGGER 102
#define IDC_RADIO1 1002
#define IDC_RADIO2 1003
#define IDC_RADIO3 1004
#define IDC_RADIO4 1005
#define IDC_RADIO5 1006
#define IDC_HWMIX 1007
#define IDC_GFOCUS 1009
#define IDC_FSYNC 1010
#define IDC_RADIO6 1016
#define IDC_RADIO7 1018
// Next default values for new objects
//
#ifdef APSTUDIO_INVOKED
#ifndef APSTUDIO_READONLY_SYMBOLS
#define _APS_NEXT_RESOURCE_VALUE 103
#define _APS_NEXT_COMMAND_VALUE 40001
#define _APS_NEXT_CONTROL_VALUE 1011
#define _APS_NEXT_SYMED_VALUE 101
#endif
#endif
// nullAICA.cpp : Defines the entry point for the DLL application.
//
#include "types.h"
#include "arm7.h"
#include "arm_mem.h"
//called when plugin is used by emu (you should do first time init here)
s32 libARM_Init()
{
init_mem();
arm_Init();
return rv_ok;
}
//called when plugin is unloaded by emu, only if dcInit is called (eg, not called to enumerate plugins)
void libARM_Term()
{
term_mem();
//arm7_Term ?
}
//It's supposed to reset anything
void libARM_Reset(bool Manual)
{
arm_Reset();
arm_SetEnabled(false);
}
void libARM_SetResetState(u32 state)
{
arm_SetEnabled(state==0);
}
//Mainloop
void libARM_Update(u32 Cycles)
{
arm_Run(Cycles/arm_sh4_bias);
}
#include "virt_arm.h"
#if HOST_CPU==CPU_X86 && FEAT_AREC != DYNAREC_NONE
#define C_CORE
namespace VARM
{
//#define CPUReadHalfWordQuick(addr) arm_ReadMem16(addr & 0x7FFFFF)
//#define CPUReadMemoryQuick(addr) (*(u32*)(addr))
#define CPUReadByte(addr) (*(u8*)(addr))
#define CPUReadMemory(addr) (*(u32*)(addr))
#define CPUReadHalfWord(addr) (*(u16*)(addr))
#define CPUReadHalfWordSigned(addr) (*(s16*)(addr))
#define CPUWriteMemory(addr,data) (*(u32*)addr=data)