Commit e144a0ac authored by aliaspider's avatar aliaspider
Browse files

reindent all files.

parent 8d4780b8
......@@ -4,7 +4,7 @@
* (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and
* Jerremy Koot (jkoot@snes9x.com)
*
* Super FX C emulator code
* Super FX C emulator code
* (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and
* Gary Henderson.
* Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_.
......@@ -41,6 +41,8 @@
#ifndef _65c816_h_
#define _65c816_h_
#include "port.h"
#define AL A.B.l
#define AH A.B.h
#define XL X.B.l
......@@ -98,27 +100,33 @@
typedef union
{
#ifdef LSB_FIRST
struct { uint8 l,h; } PACKING B;
struct
{
uint8 l, h;
} PACKING B;
#else
struct { uint8 h,l; } PACKING B;
struct
{
uint8 h, l;
} PACKING B;
#endif
uint16 W;
uint16 W;
} ALIGN_BY_ONE pair;
typedef struct
{
uint8 PB;
uint8 DB;
pair P;
pair A;
pair D;
pair X;
pair S;
pair Y;
uint16 PC;
}PACKING SRegisters;
uint8 PB;
uint8 DB;
pair P;
pair A;
pair D;
pair X;
pair S;
pair Y;
uint16 PC;
} PACKING SRegisters;
#define Registers CPU.Regs
#define Registers CPU.Regs
//EXTERN_C struct SRegisters Registers;
#endif
This diff is collapsed.
This diff is collapsed.
......@@ -4,7 +4,7 @@
* (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and
* Jerremy Koot (jkoot@snes9x.com)
*
* Super FX C emulator code
* Super FX C emulator code
* (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and
* Gary Henderson.
* Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_.
......@@ -53,51 +53,51 @@ typedef union
typedef struct
{
int32 Cycles; // 0x00
bool8 ShowROM; // 0x04
uint8 Flags; // 0x05
uint8 KeyedChannels; // 0x06
uint8 OutPorts [4]; // 0x07
uint8 DSP [0x80]; // 0x0B
uint8 ExtraRAM [64];
uint16 Timer [3];
uint16 TimerTarget [3];
bool8 TimerEnabled [3];
bool8 TimerValueWritten [3];
}SAPU;
int32 Cycles; // 0x00
bool8 ShowROM; // 0x04
uint8 Flags; // 0x05
uint8 KeyedChannels; // 0x06
uint8 OutPorts [4]; // 0x07
uint8 DSP [0x80]; // 0x0B
uint8 ExtraRAM [64];
uint16 Timer [3];
uint16 TimerTarget [3];
bool8 TimerEnabled [3];
bool8 TimerValueWritten [3];
} SAPU;
typedef struct
{
uint8 *DirectPage; // 0x00
uint32 Address; // 0x04 c core only
uint8 *WaitAddress1; // 0x08
uint8 *WaitAddress2; // 0x0C
uint32 WaitCounter; // 0x10
uint8 *ShadowRAM; // 0x14
uint8 *CachedSamples; // 0x18
uint8 _Carry; // 0x1C c core only
uint8 _Overflow; // 0x1D c core only
uint8 Bit; // 0x1E c core only
uint8 pad0;
uint32 TimerErrorCounter; // 0x20
uint32 Scanline; // 0x24
int32 OneCycle; // 0x28
int32 TwoCycles; // 0x2C
// notaz: reordered and moved everything here, for faster context load/save
uint32 *asmJumpTab; // 0x30
uint8 *PC; // 0x34
YAndA YA; // 0x38 0x0000YYAA
uint8 P; // 0x3C flags: NODBHIZC
uint8 pad1;
uint8 pad2;
uint8 _Zero; // 0x3F Z=0, when this!=0; also stores neg flag in &0x80
uint8 X; // 0x40
uint8 S; // 0x41 stack pointer, default: 0xff
uint16 pad3;
uint8 *RAM; // 0x44
uint8 *ExtraRAM; // 0x48 shortcut to APU.ExtraRAM
}SIAPU;
uint8* DirectPage; // 0x00
uint32 Address; // 0x04 c core only
uint8* WaitAddress1; // 0x08
uint8* WaitAddress2; // 0x0C
uint32 WaitCounter; // 0x10
uint8* ShadowRAM; // 0x14
uint8* CachedSamples; // 0x18
uint8 _Carry; // 0x1C c core only
uint8 _Overflow; // 0x1D c core only
uint8 Bit; // 0x1E c core only
uint8 pad0;
uint32 TimerErrorCounter; // 0x20
uint32 Scanline; // 0x24
int32 OneCycle; // 0x28
int32 TwoCycles; // 0x2C
// notaz: reordered and moved everything here, for faster context load/save
uint32* asmJumpTab; // 0x30
uint8* PC; // 0x34
YAndA YA; // 0x38 0x0000YYAA
uint8 P; // 0x3C flags: NODBHIZC
uint8 pad1;
uint8 pad2;
uint8 _Zero; // 0x3F Z=0, when this!=0; also stores neg flag in &0x80
uint8 X; // 0x40
uint8 S; // 0x41 stack pointer, default: 0xff
uint16 pad3;
uint8* RAM; // 0x44
uint8* ExtraRAM; // 0x48 shortcut to APU.ExtraRAM
} SIAPU;
EXTERN_C SAPU APU;
......@@ -106,51 +106,51 @@ EXTERN_C SIAPU IAPU;
STATIC inline void S9xAPUUnpackStatus()
{
IAPU._Zero =((IAPU.P & Zero) == 0) | (IAPU.P & Negative);
if (!Settings.asmspc700)
{
IAPU._Carry = (IAPU.P & Carry);
IAPU._Overflow = (IAPU.P & Overflow);
}
IAPU._Zero = ((IAPU.P & Zero) == 0) | (IAPU.P & Negative);
if (!Settings.asmspc700)
{
IAPU._Carry = (IAPU.P & Carry);
IAPU._Overflow = (IAPU.P & Overflow);
}
}
STATIC inline void S9xAPUPackStatus()
{
if (Settings.asmspc700)
{
IAPU.P &= ~(Zero | Negative);
if(!IAPU._Zero) IAPU.P |= Zero;
if(IAPU._Zero & 0x80) IAPU.P |= Negative;
}
else
{
IAPU.P &= ~(Zero | Negative | Carry | Overflow);
if(IAPU._Carry) IAPU.P |= Carry;
if(!IAPU._Zero) IAPU.P |= Zero;
if(IAPU._Overflow) IAPU.P |= Overflow;
if(IAPU._Zero & 0x80) IAPU.P |= Negative;
}
{
if (Settings.asmspc700)
{
IAPU.P &= ~(Zero | Negative);
if (!IAPU._Zero) IAPU.P |= Zero;
if (IAPU._Zero & 0x80) IAPU.P |= Negative;
}
else
{
IAPU.P &= ~(Zero | Negative | Carry | Overflow);
if (IAPU._Carry) IAPU.P |= Carry;
if (!IAPU._Zero) IAPU.P |= Zero;
if (IAPU._Overflow) IAPU.P |= Overflow;
if (IAPU._Zero & 0x80) IAPU.P |= Negative;
}
}
START_EXTERN_C
void S9xResetAPU (void);
bool8 S9xInitAPU ();
void S9xDeinitAPU ();
void S9xDecacheSamples ();
int S9xTraceAPU ();
int S9xAPUOPrint (char *buffer, uint16 Address);
void S9xSetAPUControl (uint8 byte);
void S9xSetAPUDSP (uint8 byte);
uint8 S9xGetAPUDSP ();
void S9xSetAPUTimer (uint16 Address, uint8 byte);
void S9xOpenCloseSoundTracingFile (bool8);
void S9xPrintAPUState ();
extern int32 S9xAPUCycles [256]; // Scaled cycle lengths
extern int32 S9xAPUCycleLengths [256]; // Raw data.
extern void (*S9xApuOpcodes [256]) (void);
extern void (*S9xApuOpcodesReal [256]) (void);
void S9xResetAPU(void);
bool8 S9xInitAPU();
void S9xDeinitAPU();
void S9xDecacheSamples();
int S9xTraceAPU();
int S9xAPUOPrint(char* buffer, uint16 Address);
void S9xSetAPUControl(uint8 byte);
void S9xSetAPUDSP(uint8 byte);
uint8 S9xGetAPUDSP();
void S9xSetAPUTimer(uint16 Address, uint8 byte);
void S9xOpenCloseSoundTracingFile(bool8);
void S9xPrintAPUState();
extern int32 S9xAPUCycles [256]; // Scaled cycle lengths
extern int32 S9xAPUCycleLengths [256]; // Raw data.
extern void (*S9xApuOpcodes [256])(void);
extern void (*S9xApuOpcodesReal [256])(void);
END_EXTERN_C
......
......@@ -2,27 +2,26 @@
#include "spc700.h"
#include "apu.h"
void S9xAPUSetByteFFtoF0 (uint8 val, uint32 Address)
void S9xAPUSetByteFFtoF0(uint8 val, uint32 Address)
{
if (Address >= 0xf4 && Address <= 0xf7)
APU.OutPorts [Address - 0xf4] = val;
else
if (Address < 0xfd)
{
IAPU.RAM [Address] = val;
if (Address >= 0xfa)
{
if (val == 0)
APU.TimerTarget [Address - 0xfa] = 0x100;
else
APU.TimerTarget [Address - 0xfa] = val;
}
}
if (Address >= 0xf4 && Address <= 0xf7)
APU.OutPorts [Address - 0xf4] = val;
else if (Address < 0xfd)
{
IAPU.RAM [Address] = val;
if (Address >= 0xfa)
{
if (val == 0)
APU.TimerTarget [Address - 0xfa] = 0x100;
else
APU.TimerTarget [Address - 0xfa] = val;
}
}
}
void S9xAPUSetByteFFC0 (uint8 val, uint32 Address)
void S9xAPUSetByteFFC0(uint8 val, uint32 Address)
{
APU.ExtraRAM [Address - 0xffc0] = val;
if (!APU.ShowROM) IAPU.RAM [Address] = val;
APU.ExtraRAM [Address - 0xffc0] = val;
if (!APU.ShowROM) IAPU.RAM [Address] = val;
}
......@@ -4,7 +4,7 @@
* (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and
* Jerremy Koot (jkoot@snes9x.com)
*
* Super FX C emulator code
* Super FX C emulator code
* (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and
* Gary Henderson.
* Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_.
......@@ -47,7 +47,7 @@ extern uint8 W4;
extern uint8 APUROM[64];
END_EXTERN_C
static INLINE uint8 S9xAPUGetByteZ (uint8 Address)
static INLINE uint8 S9xAPUGetByteZ(uint8 Address)
{
if (Address >= 0xf0 && IAPU.DirectPage == IAPU.RAM)
{
......@@ -58,50 +58,47 @@ static INLINE uint8 S9xAPUGetByteZ (uint8 Address)
return (t);
}
else if (Address == 0xf3)
return (S9xGetAPUDSP ());
return (S9xGetAPUDSP());
return (IAPU.RAM [Address]);
}
return (IAPU.DirectPage [Address]);
}
static INLINE void S9xAPUSetByteZ (uint8 val, uint8 Address)
static INLINE void S9xAPUSetByteZ(uint8 val, uint8 Address)
{
if (Address >= 0xf0 && IAPU.DirectPage == IAPU.RAM)
{
if (Address == 0xf3)
S9xSetAPUDSP (val);
else
if (Address >= 0xf4 && Address <= 0xf7)
APU.OutPorts [Address - 0xf4] = val;
else
if (Address == 0xf1)
S9xSetAPUControl (val);
S9xSetAPUDSP(val);
else if (Address >= 0xf4 && Address <= 0xf7)
APU.OutPorts [Address - 0xf4] = val;
else if (Address == 0xf1)
S9xSetAPUControl(val);
else if (Address < 0xfd)
{
IAPU.RAM [Address] = val;
if (Address >= 0xfa)
{
if (val == 0)
APU.TimerTarget [Address - 0xfa] = 0x100;
else
if (Address < 0xfd)
{
IAPU.RAM [Address] = val;
if (Address >= 0xfa)
{
if (val == 0)
APU.TimerTarget [Address - 0xfa] = 0x100;
else
APU.TimerTarget [Address - 0xfa] = val;
}
}
APU.TimerTarget [Address - 0xfa] = val;
}
}
}
else
IAPU.DirectPage [Address] = val;
}
static INLINE uint8 S9xAPUGetByte (uint32 Address)
static INLINE uint8 S9xAPUGetByte(uint32 Address)
{
Address &= 0xffff;
if (Address <= 0xff && Address >= 0xf3)
{
if (Address == 0xf3)
return (S9xGetAPUDSP ());
return (S9xGetAPUDSP());
if (Address >= 0xfd)
{
uint8 t = IAPU.RAM [Address];
......@@ -113,32 +110,29 @@ static INLINE uint8 S9xAPUGetByte (uint32 Address)
return (IAPU.RAM [Address]);
}
static INLINE void S9xAPUSetByte (uint8 val, uint32 Address)
static INLINE void S9xAPUSetByte(uint8 val, uint32 Address)
{
Address &= 0xffff;
if (Address <= 0xff && Address >= 0xf0)
{
if (Address == 0xf3)
S9xSetAPUDSP (val);
else
if (Address >= 0xf4 && Address <= 0xf7)
APU.OutPorts [Address - 0xf4] = val;
else
if (Address == 0xf1)
S9xSetAPUControl (val);
S9xSetAPUDSP(val);
else if (Address >= 0xf4 && Address <= 0xf7)
APU.OutPorts [Address - 0xf4] = val;
else if (Address == 0xf1)
S9xSetAPUControl(val);
else if (Address < 0xfd)
{
IAPU.RAM [Address] = val;
if (Address >= 0xfa)
{
if (val == 0)
APU.TimerTarget [Address - 0xfa] = 0x100;
else
if (Address < 0xfd)
{
IAPU.RAM [Address] = val;
if (Address >= 0xfa)
{
if (val == 0)
APU.TimerTarget [Address - 0xfa] = 0x100;
else
APU.TimerTarget [Address - 0xfa] = val;
}
}
APU.TimerTarget [Address - 0xfa] = val;
}
}
}
else
{
......
......@@ -6,32 +6,32 @@
({ uint32_t *dst = (_dst); register uint32_t c __asm__ ("r7") = (_c); int count = (_count); register uint32_t dummy0 __asm__ ("r4"), dummy1 __asm__ ("r5"), dummy2 __asm__ ("r6"); \
__asm__ __volatile__ ( \
" cmp %[count], #4\n" \
" blt 2f\n" \
" blt 2f\n" \
" mov %[dummy0], %[c]\n" \
" tst %[dst], #4\n" \
" strne %[c], [%[dst]], #4\n" \
" subne %[count], %[count], #1\n" \
" tst %[dst], #8\n" \
" stmneia %[dst]!, {%[dummy0], %[c]}\n" \
" subne %[count], %[count], #2\n" \
" tst %[dst], #4\n" \
" strne %[c], [%[dst]], #4\n" \
" subne %[count], %[count], #1\n" \
" tst %[dst], #8\n" \
" stmneia %[dst]!, {%[dummy0], %[c]}\n" \
" subne %[count], %[count], #2\n" \
" mov %[dummy1], %[c]\n" \
" mov %[dummy2], %[c]\n" \
"1:\n"\
" subs %[count], %[count], #4\n" \
" stmgeia %[dst]!, {%[dummy0], %[dummy1], %[dummy2], %[c]}\n" \
" bge 1b\n" \
" add %[count], %[count], #4\n" \
"2:\n"\
" subs %[count], %[count], #1\n" \
" strge %[c], [%[dst]], #4\n" \
" subs %[count], %[count], #1\n" \
" strge %[c], [%[dst]], #4\n" \
" subs %[count], %[count], #1\n" \
" strge %[c], [%[dst]], #4\n" \
"\n" \
: [dst] "+&r" (dst), [count] "+&r" (count), [dummy0] "=&r" (dummy0), [dummy1] "=&r" (dummy1), [dummy2] "=&r" (dummy2), [c] "+&r" (c) \
: \
: "cc", "memory" \
"1:\n"\
" subs %[count], %[count], #4\n" \
" stmgeia %[dst]!, {%[dummy0], %[dummy1], %[dummy2], %[c]}\n" \
" bge 1b\n" \
" add %[count], %[count], #4\n" \
"2:\n"\
" subs %[count], %[count], #1\n" \
" strge %[c], [%[dst]], #4\n" \
" subs %[count], %[count], #1\n" \
" strge %[c], [%[dst]], #4\n" \
" subs %[count], %[count], #1\n" \
" strge %[c], [%[dst]], #4\n" \
"\n" \
: [dst] "+&r" (dst), [count] "+&r" (count), [dummy0] "=&r" (dummy0), [dummy1] "=&r" (dummy1), [dummy2] "=&r" (dummy2), [c] "+&r" (c) \
: \
: "cc", "memory" \
); _dst; \
})
......@@ -39,43 +39,43 @@
({ uint16_t *dst = (_dst); register uint16_t c __asm__ ("r7") = (_c); int count = (_count); register uint32_t dummy0 __asm__ ("r4"), dummy1 __asm__ ("r5"), dummy2 __asm__ ("r6"); \
__asm__ __volatile__ ( \
" cmp %[count], #2\n" \
" blt 3f\n" \
/* Alignment is known to be at least 16-bit */ \
" blt 3f\n" \
/* Alignment is known to be at least 16-bit */ \
" tst %[dst], #2\n" \
" strneh %[c], [%[dst]], #2\n" \
" subne %[count], %[count], #1\n" \
/* Now we are 32-bit aligned (need to upgrade 'c' to 32-bit )*/ \
" strneh %[c], [%[dst]], #2\n" \
" subne %[count], %[count], #1\n" \
/* Now we are 32-bit aligned (need to upgrade 'c' to 32-bit )*/ \
" orr %[c], %[c], %[c], asl #16\n" \
" mov %[dummy0], %[c]\n" \
" cmp %[count], #8\n" \
" blt 2f\n" \
" tst %[dst], #4\n" \
" strne %[c], [%[dst]], #4\n" \
" subne %[count], %[count], #2\n" \
" tst %[dst], #8\n" \
" stmneia %[dst]!, {%[dummy0], %[c]}\n" \
" subne %[count], %[count], #4\n" \
/* Now we are 128-bit aligned */ \
" blt 2f\n" \
" tst %[dst], #4\n" \
" strne %[c], [%[dst]], #4\n" \
" subne %[count], %[count], #2\n" \
" tst %[dst], #8\n" \
" stmneia %[dst]!, {%[dummy0], %[c]}\n" \
" subne %[count], %[count], #4\n" \
/* Now we are 128-bit aligned */ \
" mov %[dummy1], %[c]\n" \
" mov %[dummy2], %[c]\n" \
"1:\n" /* Copy 4 32-bit values per loop iteration */ \
" subs %[count], %[count], #8\n" \
" stmgeia %[dst]!, {%[dummy0], %[dummy1], %[dummy2], %[c]}\n" \
" bge 1b\n" \
" add %[count], %[count], #8\n" \
"2:\n" /* Copy up to 3 remaining 32-bit values */ \
" tst %[count], #4\n" \
" stmneia %[dst]!, {%[dummy0], %[c]}\n" \
" tst %[count], #2\n" \
" strne %[c], [%[dst]], #4\n" \
" and %[count], %[count], #1\n" \
"3:\n" /* Copy up to 1 remaining 16-bit value */ \
" subs %[count], %[count], #1\n" \
" strgeh %[c], [%[dst]], #2\n" \
"\n" \
: [dst] "+&r" (dst), [count] "+&r" (count), [dummy0] "=&r" (dummy0), [dummy1] "=&r" (dummy1), [dummy2] "=&r" (dummy2), [c] "+&r" (c) \
: \
: "cc", "memory" \
"1:\n" /* Copy 4 32-bit values per loop iteration */ \
" subs %[count], %[count], #8\n" \
" stmgeia %[dst]!, {%[dummy0], %[dummy1], %[dummy2], %[c]}\n" \
" bge 1b\n" \
" add %[count], %[count], #8\n" \
"2:\n" /* Copy up to 3 remaining 32-bit values */ \
" tst %[count], #4\n" \
" stmneia %[dst]!, {%[dummy0], %[c]}\n" \
" tst %[count], #2\n" \
" strne %[c], [%[dst]], #4\n" \
" and %[count], %[count], #1\n" \
"3:\n" /* Copy up to 1 remaining 16-bit value */ \
" subs %[count], %[count], #1\n" \
" strgeh %[c], [%[dst]], #2\n" \
"\n" \
: [dst] "+&r" (dst), [count] "+&r" (count), [dummy0] "=&r" (dummy0), [dummy1] "=&r" (dummy1), [dummy2] "=&r" (dummy2), [c] "+&r" (c) \
: \
: "cc", "memory" \
); _dst;\
})
......@@ -83,32 +83,32 @@
({ uint32_t *dst = (_dst); uint32_t *src = (_src); int count = (_count); \
__asm__ __volatile__ ( \
" cmp %[count], #4\n" \
" blt 2f\n" \
" tst %[dst], #4\n" \
" ldrne r4, [%[src]], #4\n" \
" strne r4, [%[dst]], #4\n" \
" subne %[count], %[count], #1\n" \
" tst %[dst], #8\n" \
" ldmneia %[src]!, {r4-r5}\n" \
" stmneia %[dst]!, {r4-r5}\n" \
" subne %[count], %[count], #2\n" \
"1:\n" \
" subs %[count], %[count], #4\n" \
" ldmgeia %[src]!, {r4-r7}\n" \
" stmgeia %[dst]!, {r4-r7}\n" \
" bge 1b\n" \
" add %[count], %[count], #4\n" \
"2:\n" \
" tst %[count], #2\n" \
" ldmneia %[src]!, {r4-r5}\n" \
" stmneia %[dst]!, {r4-r5}\n" \
" tst %[count], #1\n" \
" ldrne r4, [%[src]], #4\n" \
" strne r4, [%[dst]], #4\n" \
"\n" \
: [dst] "+&r" (dst), [src] "+&r" (src), [count] "+&r" (count) \
: \
: "r4", "r5", "r6", "r7", "cc", "memory" \
" blt 2f\n" \
" tst %[dst], #4\n" \
" ldrne r4, [%[src]], #4\n" \
" strne r4, [%[dst]], #4\n" \
" subne %[count], %[count], #1\n" \
" tst %[dst], #8\n" \
" ldmneia %[src]!, {r4-r5}\n" \
" stmneia %[dst]!, {r4-r5}\n" \
" subne %[count], %[count], #2\n" \
"1:\n" \
" subs %[count], %[count], #4\n" \
" ldmgeia %[src]!, {r4-r7}\n" \
" stmgeia %[dst]!, {r4-r7}\n" \